Part of Advances in Neural Information Processing Systems 4 (NIPS 1991)
Alice Chiang, Michael Chuang, Jeffrey LaFranchise
A CCD-based processor that we call the NNC2 is presented. The NNC2 implements a fully connected 192-input, 32-output two-layer network and can be cascaded to form multilayer networks or used in parallel for ad(cid:173) ditional input or output nodes. The device computes 1.92 x 109 connec(cid:173) tions/sec when clocked at 10 MHz. Network weights can be specified to six bits of accuracy and are stored on-chip in programmable digital memories. A neural network pattern recognition system using NNC2 and CCD im(cid:173) age feature extractor (IFE) devices is described. Additionally, we report a CCD output circuit that exploits inherent nonlinearities in the charge injection process to realize an adjustable-threshold sigmoid in a chip area of 40 x 80 J.tlU2 .