Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing

Part of Advances in Neural Information Processing Systems 8 (NIPS 1995)

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Tadashi Shibata, Tsutomu Nakai, Tatsuo Morimoto, Ryu Kaihara, Takeo Yamashita, Tadahiro Ohmi


A unique architecture of winner search hardware has been de(cid:173) veloped using a novel neuron-like high functionality device called Neuron MOS transistor (or vMOS in short) [1,2] as a key circuit element. The circuits developed in this work can find the location of the maximum (or minimum) signal among a number of input data on the continuous-time basis, thus enabling real-time winner tracking as well as fully-parallel sorting of multiple input data. We have developed two circuit schemes. One is an ensemble of self(cid:173) loop-selecting v M OS ring oscillators finding the winner as an oscil(cid:173) lating node. The other is an ensemble of vMOS variable threshold inverters receiving a common ramp-voltage for competitive excita(cid:173) tion where data sorting is conducted through consecutive winner search actions. Test circuits were fabricated by a double-polysilicon CMOS process and their operation has been experimentally veri(cid:173) fied.