{"title": "AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems", "book": "Advances in Neural Information Processing Systems", "page_first": 1217, "page_last": 1224, "abstract": "", "full_text": "AER Building Blocks for Multi-Layer Multi-Chip\n\nNeuromorphic Vision Systems\n\nR. Serrano-Gotarredona1, M. Oster2, P. Lichtsteiner2, A. Linares-Barranco4, R. Paz-\nVicente4, F. G\u00f3mez-Rodr\u00edguez4, H. Kolle Riis3, T. Delbr\u00fcck2, S. C. Liu2, S. Zahnd2,\n\nA. M. Whatley2, R. Douglas2, P. H\u00e4\ufb02iger3, G. Jimenez-Moreno4, A. Civit4, T.\n\nSerrano-Gotarredona1, A. Acosta-Jim\u00e9nez1, B. Linares-Barranco1\n\n1Instituto de Microelectr\u00f3nica de Sevilla (IMSE-CNM-CSIC) Sevilla Spain, 2Institute of\nNeuroinformatics (INI-ETHZ) Zurich Switzerland, 3University of Oslo Norway (UIO),\n\n4University of Sevilla Spain (USE).\n\nAbstract\n\nA 5-layer neuromorphic vision processor whose\ncomponents\ncommunicate spike events asychronously using the address-event-\nrepresentation (AER) is demonstrated. The system includes a retina\nchip, two convolution chips, a 2D winner-take-all chip, a delay line\nchip, a learning classi\ufb01er chip, and a set of PCBs for computer\ninterfacing and address space remappings. The components use a\nmixture of analog and digital computation and will learn to classify\ntrajectories of a moving object. A complete experimental setup and\nmeasurements results are shown.\n\n1  Introduction\n\nThe Address-Event-Representation (AER) is an event-driven asynchronous inter-chip\ncommunication technology for neuromorphic systems [1][2]. Senders (e.g. pixels or\nneurons) asynchronously generate events that are represented on the AER bus by the\nsource addresses. AER systems can be easily expanded. The events can be merged with\nevents from other senders and broadcast to multiple receivers [3]. Arbitrary connections,\nremappings and transformations can be easily performed on these digital addresses.\nA potentially huge advantage of AER systems is that computation is event driven and thus\ncan be very fast and ef\ufb01cient. Here we describe a set of AER building blocks and how we\nassembled them into a prototype vision system that learns to classify trajectories of a\nmoving object. All modules communicate asynchronously using AER. The building\nblocks and demonstration system have been developed in the EU funded research project\nCAVIAR (Convolution AER VIsion Architecture for Real-time). The building blocks\n(Fig. 1) consist of: (1) a retina loosely modeled on the magnocellular pathway that\nresponds to brightness changes, (2) a convolution chip with programmable convolution\nkernel of arbitrary shape and size, (3) a multi-neuron 2D competition chip, (4) a spatio-\ntemporal pattern classi\ufb01cation learning module, and (5) a set of FPGA-based PCBs for\naddress remapping and computer interfaces.\nUsing these AER building blocks and tools we built the demonstration vision system\nshown schematically in Fig. 1, that detects a moving object and learns to classify its\n\n\fFig. 1: Demonstration AER vision system\n\ntrajectories. It has a front end retina, followed by an array of convolution chips, each\nprogrammed to detect a speci\ufb01c feature with a given spatial scale. The competition or\n\u2018object\u2019 chip selects the most salient feature and scale. A spatio-temporal pattern\nclassi\ufb01cation module categorizes trajectories of the object chip outputs.\n\n2  Retina\n\nchanges\n\nin image\n\nintensity\n\n[8]. These\n\naddress-events\n\nBiological vision uses asynchronous events (spikes) delivered from the retina. The stream\nof events encodes dynamic scene contrast. Retinas are optimized to deliver relevant\ninformation and to discard redundancy. CAVIAR\u2019s input is a dynamic visual scene. We\ndeveloped an AER silicon retina chip \u2018TMPDIFF\u2019 that generates events corresponding to\nare broadcast\nrelative\nasynchronously on a shared digital bus to the convolution chips. Static scenes produce no\noutput. The events generated by TMPDIFF represent relative changes in intensity that\nexceed a user-de\ufb01ned threshold and are ON or OFF type depending on the sign of the\nchange since the last event. This silicon retina loosely models the magnocellular retinal\npathway.\nThe front-end of the pixel core (see Fig. 2a) is an active unity-gain logarithmic\nphotoreceptor that can be self-biased by the average photocurrent [7]. The active feedback\nspeeds up the response compared to a passive log photoreceptor and greatly increases\nbandwidth at low illumination. The photoreceptor output is buffered to a voltage-mode\ncapacitive-feedback ampli\ufb01er with closed-loop gain set by a well-matched capacitor ratio.\nThe ampli\ufb01er is balanced after transmission of each event by the AER handshake. ON and\nOFF events are detected by the comparators that follow. Mismatch of the event threshold\nis determined by only 5 transistors and is effectively further reduced by the gain of the\nampli\ufb01er. Much higher contrast resolution than in previous work [6] is obtained by using\nthe excellent matching between capacitors to form a self-clocked switched-capacitor\nchange ampli\ufb01er, allowing for operation with scene contrast down to about 20%. A chip\nphoto is shown in Fig. 2b.\n\n(a)\n\n(b)\n\nFig. 2.  Retina. a) core of pixel circuit, b) chip photograph.\n\n\fLine Buffer & Column Arbiter\n\nr\ne\nd\no\nc\ne\nD\n\u2212\ny\n\n(a)\n\n(x,y)\n\nMonostable\n\nx\u2212neighbourhood\n\nPixel Array\n\nAER\nout\n\nr\ne\nt\ni\nb\nr\nA\n\u2212\nw\no\nR\n\nHigh\nSpeed\nClock\n\nControl\nBlock\n\nAddress\nRqst\nAck\n\nI/O\n\n(b)\n\nKernel\u2212RAM\n\npixel array\n\nControl\n\nX-neighb.\n\nkernel-RAM\n\n2\n\n0\n\n\u22122\n\n\u22124\n\n0\n\n5\n\n10\n\n15\n\n20\n\n25\n\n30\n\n35\n\n0\n\n5\n\n10\n\n15\n\n(c)\n\n20\n\n25\n\n30\n\n35\n\n(d)\n\n5\n\n0\n\n\u22125\n\n35\n\n30\n\n25\n\n20\n\n15\n\n10\n\n5\n\n25\n\n20\n\n15\n\n10\n\n35\n\n30\n\n0\n\n0\n\n5\n\nFig. 3. Convolution chip (a) architecture of the convolution chip. (b) microphotograph of\n\nfabricated chip. (c) kernel for detecting circumferences of radius close to 4 pixels and (d) close to 9\n\npixels.\n\nTMPDIFF has 64x64 pixels, each with 2 outputs (ON and OFF), which are communicated\noff-chip on a 16-bit AER bus. It is fabricated in a 0.35\u00b5m process. Each pixel is\n40x40 \u00b5m2 and has 28 transistors and 3 capacitors. The operating range is at least 5\ndecades and minimum scene illumination with f/1.4 lens is less than 10 lux.\n\n3  Convolution Chip\n\nThe convolution chip is an AER transceiver with an array of event integrators. Foreach\nincoming event, integrators within a projection \ufb01eld around the addressed pixel compute a\nweighted event integration. The weight of this integration is de\ufb01ned by the convolution\nkernel [4]. This event-driven computation puts the kernel onto the integrators.\nFig. 3a shows the block diagram of the convolution chip. The main parts of the chip are:\n(1) An array of 32x32 pixels. Each pixel contains a binary weighted signed current source\nand an integrate-and-\ufb01re signed integrator [5]. The current source is controlled by the\nkernel weight read from the RAM and stored in a dynamic register. (2) A 32x32 kernel\nRAM. Each kernel weight value is stored with signed 4-bit resolution. (3) A digital\ncontroller handles all sequence of operations. (4) A monostable. For each incoming event,\nit generates a pulse of \ufb01xed duration that enables the integration simultaneously in all the\npixels. (5) X-Neighborhood Block. This block performs a displacement of the kernel in\nthe x direction. (6) Arbitration and decoding circuitry that generate the output address\nevents. It uses Boahen\u2019s burst mode fully parallel AER [2].\nThe chip operation sequence is as follows: (1) Each time an input address event is\nreceived, the digital control block stores the (x,y) address and acknowledges reception of\nthe event. (2) The control block computes the x-displacement that has to be applied to the\nkernel and the limits in the y addresses where the kernel has to be copied. (3) The\nAfterwards, the control block generates signals that control on a row-by-row basis the\ncopy of the kernel to the corresponding rows in the pixel array. (4) Once the kernel copy is\n\ufb01nished, the control block activates the generation of a monostable pulse. This way, in\neach pixel a current weighted by the corresponding kernel weight is integrated during a\n\ufb01xed time interval. Afterwards, kernel weights in the pixels are erased. (5) When the\nintegrator voltage in a pixel reaches a threshold, that pixel asynchronously sends an event,\nwhich is arbitrated and decoded in the periphery of the array. The pixel voltage is reset\nupon reception of the acknowledge from the periphery.\n\n\fA prototype convolution chip has been fabricated in a CMOS 0.35\u00b5m process. Both the\nsize of the pixel array and the size of the kernel storage RAM are 32x32. The input address\nspace can be up to 128x128. In the experimental setup of Section 7, the 64x64 retina\noutput is fed to the convolution chip, whose pixel array addresses are centered on that of\nthe retina. The pixel size is 92.5\u00b5m x 95\u00b5m. The total chip area is 5.4x4.2 mm2. Fig. 3b\nshows the microphotograph of the fabricated chip. AER events can be fed-in up to a peak\nrate of 50 Mevent/s. Output event rate depends on kernel lines nk. The measured output\nAER peak delay is (40 + 20 x nk) ns/event.\n\n4  Competition \u2018Object\u2019 Chip\n\nThis AER transceiver chip consists of a group of VLSI integrate-and-\ufb01re neurons with\nvarious types of synapses [9]. It reduces the dimensionality of the input space by\npreserving the strongest input and suppressing all other inputs. The strongest input is\ndetermined by con\ufb01guring the architecture on the \u2019Object\u2019 chip as a spiking winner-take-\nall network. Each convolution chip convolves the output spikes of the retina with its\npreprogrammed feature kernel (in our example, this kernel consists of a ring \ufb01lter of a\nparticular resolution). The \u2019Object\u2019 chip receives the outputs of several convolution chips\nand computes the winner (strongest input) in two dimensions. First, it determines the\nstrongest input in each feature map and in addition, it determines the strongest feature.\nThe computation to determine the strongest input in each feature map is carried out using\na two-dimensional winner-take-all circuit as shown in Fig. 4. The network is con\ufb01gured so\nthat it implements a hard winner-take-all, that is, only one neuron is active at a time. The\nactivity of the winner is proportional to the winner\u2019s input activity.\nThe winner-take-all circuit can reliably select the winner given a difference of input \ufb01ring\nrate of only 10% assuming that it receives input spike trains having a regular \ufb01ring rate\n[10]. Each excitatory input spike charges the membrane of the post-synaptic neuron until\none neuron in the array--the winner--reaches threshold and is reset. All other neurons are\nthen inhibited via a global inhibitory neuron which is driven by all the excitatory neurons.\nSelf-excitation provides hysteresis for the winning neuron by facilitating the selection of\nthis neuron as the next winner.\nBecause of the moving stimulus, the network has to determine the winner using an\nestimate of the instantaneous input \ufb01ring rates. The number of spikes that the neuron must\nintegrate before eliciting an output spike can be adjusted by varying the ef\ufb01cacies of the\ninput synapses.\nTo determine the winning feature, we use the activity of the global inhibitory neuron\n(which re\ufb02ects the activity of the strongest input within a feature map) of each feature map\nin a second layer of competition. By adding a second global inhibitory neuron to each\nfeature map and by driving this neuron through the outputs of the \ufb01rst global inhibitory\nneurons of all feature maps, only the strongest feature map will survive. The output of the\nobject chip will be spikes encoding the spatial location of the stimulus and the identity of\nthe winning feature. (In the characterization shown in Section 7, the global competition\nwas disabled, so both objects could be simultaneously localized by the object chip).\nWe integrated the winner-take-all circuits for four feature maps on a single chip with a\ntotal of 16x16 neurons; each feature uses an 8x8 array. The chip was fabricated in a\n0.35 \u00b5m CMOS process with an area of 8.5 mm2.\n\n5  Learning Spatio-Temporal Pattern Classi\ufb01cation\n\nThe last step of data reduction in the CAVIAR demonstrator is a subsystem that learns to\nclassify the spatio-temporal patterns provided by the object chip. It consists of three\n\n\fright\nhalf\nvisual\nfield\n\nleft\nhalf\nvisual\nfield\n\ndelay line chip\n\n3\n\n\u2206 t\n\n4\n\n\u2206 t\n\n5\n\n0\n\n\u2206 t\n\n1\n\n\u2206 t\n\n2\n\nAER mapper\n\ncompetitive Hebbian\nlearning chip\n\n.....\n\nFig. 4: Architecture of \u2019Object\u2019 chip con\ufb01gured\nfor competition within two feature maps and\n\ncompetition across the two feature maps.\n\nFig. 5: System setup for learning direction of\n\nmotion\n\ncomponents: a delay line chip, a competitive Hebbian learning chip [11], and an AER\nmapper that connects the two. The task of the delay line chip is to project the temporal\ndimension into a spatial dimension. The competitive Hebbian learning chip will then learn\nto classify the resulting patterns. The delay line chip consists of one cascade of 880 delay\nelements. 16 monostables in series form one delay element. The output of every delay\nelement produces an output address event. A pulse can be inserted at every delay-element\nby an input address event. The cascade can be programmed to be interrupted or connected\nbetween any two subsequent delay-elements. The associative Hebbian learning chip\nconsists of 32 neurons with 64 learning synapses each. Each synapse includes learning\ncircuitry with a weak multi-level memory cell for spike-based learning [11].\nA simple example of how this system may be con\ufb01gured is depicted in Fig. 5: the mapper\nbetween the object chip and the delay line chip is programmed to project all activity from\nthe left half of the \ufb01eld of vision onto the input of one delay line, and from the right half of\nvision onto another. The mapper between the delay line chip and the competitive Hebbian\nlearning chip taps these two delay lines at three different delays and maps these 6 outputs\nonto 6 synapses of each of the 32 neurons in the competitive Hebbian learning chip. This\ncon\ufb01guration lets the system learn the direction of motion.\n\n(a)\n\n(b)\n\n(c)\n\n(d)\n\nFig. 6: Developed AER interfacing PCBs. (a) PCI-AER, (b) USB-AER, (c) AER-switch, (d) mini-USB\n\n\fPCI\u2212AER\nMonitor\n\nConvolution\n\nAER\n\nchip\n\nConvolution\n\nAER\n\nchip\n\n7\n\n5\n\n6\n\n2\n\nAER\nmotion\nretina\n\n3\n\n4\n\nUSB\nAER\nmapper\n\nAER\nSplitter\n\n(a)\n\n(b)\n\n8\n\nUSB\nAER\nmonitor\n\nUSB\nAER\nmonitor\n\n9\n\n7\n\n10\n\nAER\nMerger\n\n11\n\nUSB\nAER\nmapper\n\n12\n\nAER\nobject\nchip\n\n13\n\nUSB\nAER\nmonitor\n\n14\n\nUSB\nAER\nmapper\n\n15\n\nAER\ndelay\nline\nchip\n\n16\n\nUSB\nAER\nmapper\n\n17\n\nAER\nlearning\n\nchip\n\n10\n\n8\n\n11\n\n17\n\n15\n\n16\n\n14\n\n13\n\n12\n\n1\n\n2\n\n5\n\n9\n\n3\n\n4\n\n6\n\nFig. 7: Experimental setup of multi-layered AER vision system for ball tracking (white boxes include\ncustom designed chips, blue boxes are interfacing PCBs). (a) block diagram, (b) photograph of setup.\n\n6  Computer Interfaces\n\nWhen developing and tuning complex hierarchical multi-chips AER systems it is crucial\nto have available proper computer interfaces for (a) reading AER traf\ufb01c and visualizing it,\nand (b) for injecting synthesized or recorded AER traf\ufb01c into AER buses. We developed\nseveral solutions. Fig. 6(a) shows a PCI-AER interfacing PCB capable of transmitting\nAER streams from within the computer or, vice versa, capturing them from an AER bus\nand into computer memory. It uses a Spartan-II FPGA, and can achieve a peak rate of\n15 Mevent/s using PCI mastering. Fig. 5(b) shows a USB-AER board that does not require\na PCI slot and can be controlled through a USB port. It uses a Spartan II 200 FPGA with a\nSilicon Labs C8051F320 microcontroller. Depending on the FPGA \ufb01rmware, it can be\nused to perform \ufb01ve different functions: (a) transform sequence of frames into AER in real\ntime [13], (b) histogram AER events into sequences of frames in real time, (c) do\nremappings of addresses based on look-up-tables, (d) capture timestamped events for off-\nline analysis, (e) reproduce time-stamped sequences of events in real time. This board can\nalso work without a USB connection (stand-alone mode) by loading the \ufb01rmware through\nMMC/SD cards, used in commercial digital cameras. This PCB can handle AER traf\ufb01c of\nup to 25 Mevent/s. It also includes a VGA output for visualizing histogrammed frames.\nThe third PCB, based on a simple CPLD, is shown in Fig. 6(c). It splits one AER bus into\n2, 3 or 4 buses, and vice versa, merges 2, 3 or 4 buses into a single bus, with proper\nhandling of handshaking signals. The last board in Fig. 6(d) is a lower performance but\nmore compact\nsingle-chip bus-powered USB interface based on a C8051F320\nmicrocontroller. It captures timestamped events to a computer at rates of up to 100 kevent/\ns and is particularly useful for demonstrations and \ufb01eld capture of retina output.\n\n7  Demonstration Vision System\n\nTo test CAVIAR\u2019s capabilities, we built a demonstration system that could simultaneously\ntrack two objects of different size. A block diagram of the complete system is shown in\nFig. 7(a), and a photograph of the complete experimental setup is given in Fig. 7(b). The\n\n\f(a)\n\n(b)\n(b)\n\n(c)\n\nFig. 8: Captured AER outputs\nat different stages of processing\nchain. (a) at the retina output,\n(b) at the output of the 2\nconvolution chips, (c) at the\noutput of the object chip. \u2018I\u2019\nlabels the activity of the\ninhibitory neurons.\n\ncomplete chain consisted of 17 pieces (chips and PCBs), all numbered in Fig. 7: (1) The\nrotating wheel stimulus. (2) The retina. The retina looked at a rotating disc with two solid\ncircles on it of two different radii. (3) A USB-AER board as mapper to reassign addresses\nand eliminate the polarity of brightness change. (4) A 1-to-3 splitter (one output for the\nPCI-AER board (7) to visualize the retina output, as shown in Fig. 8(a), and two outputs\nfor two convolution chips). (5-6) Two convolution chips programmed with the kernels in\nFig. 3c-d, to detect circumferences of radius 4 pixels and 9 pixels, respectively. They see\nthe complete 64x64 retina image (with recti\ufb01ed activity; polarity is ignored) but provide a\n32x32 output for only the central part of the retina image. This eliminates convolution\nedge effects. The output of each convolution chip is fed to a USB-AER board working as a\nmonitor (8-9) to visualize their outputs (Fig. 8b). The left half is for the 4-radius kernel\nand the right half for the 9-radius kernel. The outputs of the convolution chips provide the\ncenter of the circumferences only if they have radius close to 4 pixels or 9 pixels,\nrespectively. As can be seen, each convolution chip detects correctly the center of its\ncorresponding circumference, but not the other. Both chips are tuned for the same feature\nbut with different spatial scale. Both convolution chips outputs are merged onto a single\nAER bus using a merger (10) and then fed to a mapper (11) to properly reassign the\naddress and bit signs for the winner-take-all \u2018object\u2019 chip (12), which correctly decides the\ncenters of the convolution chip outputs. The object chip output is fed to a monitor (13) for\nvisualization purposes. This output is shown in Fig. 8(c). The output of this chip is\ntransformed using a mapper (14) and fed to the delay line chip (15), the outputs of which\nare fed through a mapper (16) to the learning (17) chip. The system as characterized can\nsimultaneously trach two objects of different shape; we have connected but not yet studied\ntrajectory learning and classi\ufb01cation.\n\n8  Conclusions\n\nIn terms of the number of independent components, CAVIAR demonstrates the largest\nAER system yet assembled. It consists of 5 custom neuromorphic AER chips and at least\n6 custom AER digital boards. Its functioning shows that AER can be used for assembling\ncomplex real time sensory processing systems and that relevant information about object\nsize and location can be extracted and restored through a chain of feedforward stages. The\nCAVIAR system is a useful environment to develop reusable AER infrastructure and is\ncapable of fast visual computation that is not limited by normal imager frame rate. Its\ncontinued development will result in insights about spike coding and representation.\n\nAcknowledgements\nThis work was sponsored by EU grant IST-2001-34124 (CAVIAR), and Spanish grant\nTIC-2003-08164-C03 (SAMANTA). We thank K. Boahen for sharing AER interface\n\n\ftechnology and the EU project ALAVLSI for sharing chip development and other AER\ncomputer interfaces [14].\n\nReferences\n[1] M. Sivilotti, Wiring Considerations in Analog VLSI Systems with Application to Field-\nProgrammable Networks, Ph.D. Thesis, California Institute of Technology, Pasadena CA,\n1991.\n[2] K. Boahen, \u201cPoint-to-Point Connectivity Between Neuromorphic Chips Using\nAddress Events,\u201d IEEE Trans. on Circuits and Systems Part-II, vol. 47, No. 5, pp. 416-434,\nMay 2000.\n[3] J. P. Lazzaro and J. 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Kolle Riis and P. Hae\ufb02iger, \u201cSpike based learning with weak multi-level static\nmemory,\u201d In Proc. of the IEEE Int. Symp. Circ. Syst. (ISCAS04), vol. 5, pp. 393-395,\nVancouver, Canada, May 2004.\n[12] P. H\u00e4\ufb02iger and H. Kolle Riis, \u201cA Multi-Level Static Memory Cell,\u201d In Proc. of the\nIEEE Int. Symp. Circ. Syst. (ISCAS04), vol. 1, pp. 22-25, Bangkok, Thailand, May 2003.\n[13] A. Linares-Barranco, G. Jim\u00e9nez-Moreno, B. Linares-Barranco, and A. Civit-Ballcels,\n\u201cOn Algorithmic Rate-Coded AER Generation,\u201d accepted for publication in IEEE Trans.\nNeural Networks, May 2006 (tentatively).\n[14] V. Dante, P. Del Giudice, and A. M. Whatley, \u201cPCI-AER Hardware and Software for\nInterfacing to Address-Event Based Neuromorphic Systems\u201d, The Neuromorphic\nEngineer, 2:(1) 5-6, 2005.\n\n\f", "award": [], "sourceid": 2889, "authors": [{"given_name": "R.", "family_name": "Serrano-Gotarredona", "institution": null}, {"given_name": "M.", "family_name": "Oster", "institution": null}, {"given_name": "P.", "family_name": "Lichtsteiner", "institution": null}, {"given_name": "A.", "family_name": "Linares-Barranco", "institution": null}, {"given_name": "R.", "family_name": "Paz-Vicente", "institution": null}, {"given_name": "F.", "family_name": "Gomez-Rodriguez", "institution": null}, {"given_name": "H.", "family_name": "Kolle Riis", "institution": null}, {"given_name": "T.", "family_name": "Delbruck", "institution": null}, {"given_name": "S.", "family_name": "Liu", "institution": null}, {"given_name": "S.", "family_name": "Zahnd", "institution": null}, {"given_name": "A.", "family_name": "Whatley", "institution": null}, {"given_name": "R.", "family_name": "Douglas", "institution": null}, {"given_name": "P.", "family_name": "Hafliger", "institution": null}, {"given_name": "G.", "family_name": "Jimenez-Moreno", "institution": null}, {"given_name": "A.", "family_name": "Civit", "institution": null}, {"given_name": "T.", "family_name": "Serrano-Gotarredona", "institution": null}, {"given_name": "A.", "family_name": "Acosta-Jimenez", "institution": null}, {"given_name": "B.", "family_name": "Linares-Barranco", "institution": null}]}